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dsPIC33FJ16GP101/102 AND dsPIC33FJ16MC101/102
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
FLTA1 (1,3)
FLTB1 (2,3)
PWM1L1
PWM1H1
PWM1L2
PWM1H2
PWM1L3
PWM1H3
RTCC
Pin
Type
I
I
O
O
O
O
O
O
O
Buffer
Type
ST
ST
—
—
—
—
—
—
Digital
PPS
No
No
No
No
No
No
No
No
No
PWM1 Fault A input.
PWM1 Fault B input.
PWM1 Low output 1
PWM1 High output 1
PWM1 Low output 2
PWM1 High output 2
PWM1 Low output 3
PWM1 High output 3
RTCC Alarm output.
Description
CTPLS
O
Digital
Yes CTMU Pulse Output.
CTED1
CTED2
CV REF
C1INA
C1INB
C1INC
C1IND
C1OUT
C2INA
C2INB
C2INC
C2IND
C2OUT
C3INA
C3INB
C3INC
C3IND
C3OUT
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
MCLR
AV DD
I
I
I
I
I
I
I
O
I
I
I
I
O
I
I
I
I
O
I/O
I
I/O
I
I/O
I
I/P
P
Digital
Digital
Analog
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
Analog
Analog
Analog
Analog
Digital
ST
ST
ST
ST
ST
ST
ST
P
No
No
No
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
Yes
No
No
No
No
No
No
No
No
CTMU External Edge Input 1.
CTMU External Edge Input 2.
Comparator Voltage Positive Reference Input.
Comparator 1 Positive Input A.
Comparator 1 Negative Input B.
Comparator 1 Negative Input C.
Comparator 1 Negative Input D.
Comparator 1 Output.
Comparator 2 Positive Input A.
Comparator 2 Negative Input B.
Comparator 2 Negative Input C.
Comparator 2 Negative Input D.
Comparator 2 Output.
Comparator 3 Positive Input A.
Comparator 3 Negative Input B.
Comparator 3 Negative Input C.
Comparator 3 Negative Input D.
Comparator 3 Output.
Data I/O pin for programming/debugging communication channel 1.
Clock input pin for programming/debugging communication channel 1.
Data I/O pin for programming/debugging communication channel 2.
Clock input pin for programming/debugging communication channel 2.
Data I/O pin for programming/debugging communication channel 3.
Clock input pin for programming/debugging communication channel 3.
Master Clear (Reset) input. This pin is an active-low Reset to the device.
Positive supply for analog modules. This pin must be connected at all times.
For devices without this pin, this signal is connected to V DD internally.
AV SS
P
P
No
Ground reference for analog modules. For devices without this pin, this signal
is connected to V SS internally.
V DD
V CAP
V SS
P
P
P
—
—
—
No
No
No
Positive supply for peripheral logic and I/O pins.
CPU logic filter capacitor connection.
Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
PPS = Peripheral Pin Select
Note 1:
2:
3:
An external pull-down resistor is required for the FLTA1 pin on dsPIC33FJ16MC101 (20-pin) devices.
The FLTB1 pin is not available on dsPIC33FJ16MC101 (20-pin) devices.
The PWM Fault pins are enabled during any reset event. Refer to Section 15.2 “PWM Faults” for more
information on the PWM faults.
DS70652C-page 18
Preliminary
? 2011 Microchip Technology Inc.
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